DDS calculator: tuning word, images and spurs

There is always an image

A DDS does not produce a clean sine but a staircase approximation, so the spectrum always carries an image beside the wanted signal, at fclk minus f_out. That is not a fault of any particular chip but a property of sampling. Only a low-pass filter at the output removes it — and that is exactly what gets left out most often.

The image at fclk − fout is always there; only the output filter removes it

IC	AD9850 — 125 MHz, 32 bits, 10-bit DACAD9851 — 180 MHz, 32 bits, 10-bit DACAD9833 — 25 MHz, 28 bits, 10-bit DACAD9834 — 75 MHz, 28 bits, 10-bit DACAD9910 — 1 GHz, 32 bits, 14-bit DAC
Clock frequency (MHz)
Phase accumulator width (bits)
Required output frequency (MHz)
DAC resolution (bits)
Width after phase truncation (bits)
Settings
Frequency tuning word FTW
Word in hexadecimal
Resolution
Actual frequency
Setting error
Spectrum
First image (fclk − fout)
Nyquist frequency
Practical upper limit (0.4·fclk)
Level roll-off from sinc
SFDR from DAC resolution
SFDR from phase truncation

📐 The formulas

FTW = round( f_out · 2^N / fclk )
f_actual = FTW · fclk / 2^N
Resolution Δf = fclk / 2^N

Images:

k·fclk ± f_out,   k = 1, 2, 3…
First image: fclk − f_out
Nyquist limit: fclk/2;  practical limit: 0.4·fclk

Sinc roll-off:

A(f) = sin(π·f/fclk) / (π·f/fclk)

Dynamic range:

from DAC resolution:        SFDR ≈ 6.02·b + 1.76 dB
from phase truncation to W: SFDR ≈ 6.02·(W − 1) dB

A check point (AD9850: fclk = 125 MHz, N = 32):

Δf = 0.0291 Hz. For 7.050000 MHz, FTW = 242,236,155, giving an actual frequency of 7,049,999.986 Hz (an error of −0.014 Hz). The first image is at 117.95 MHz, and the sinc roll-off is −0.046 dB.

Where this calculator stops:

• The Si5351 works differently — it is a PLL with dividers, not a DDS, and these formulas do not apply to it
• Above 0.4·fclk the image comes too close to the wanted signal and the filter becomes impractical
• SFDR from resolution is a theoretical limit; real spurs from DAC nonlinearity and coupling are usually worse
• The clock oscillator's phase noise, which transfers wholesale to the output, is not accounted for

🎯 In practice

• A VFO for a homebrew transceiver using an AD9850 or AD9834.
• Designing the output low-pass filter: the image frequency is the main input.
• Checking whether the frequency you want falls within the chip's practical range.

Practical advice:

1. A low-pass filter at the output is not optional — without it the image goes on the air.
2. Stay below 0.4·fclk: above that the filter has to be impossibly steep.
3. A DDS inherits its phase noise wholesale from the clock — do not economise there.
4. Sinc roll-off at the top of the range is normal; compensate for it with a rise in the filter or the amplifier.

© 2026 UR3PKI · CyberDev.Space · Content licensed under CC BY-NC-SA 4.0.

How to cite this calculator

UR3PKI. «DDS Calculator: Frequency Tuning Word and Spurs». CyberDev.Space. https://cyberdev.space/en/radio/calculators/others/dds/ (licence CC BY-NC-SA 4.0).

The licence lets you use this material freely, including in teaching materials, but only with attribution to the author and a link to the source.