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PLL calculator: dividers and loop filter

Why a fine step costs you noise

The noise of the reference oscillator and the phase detector is multiplied by the square of the divider ratio — that is, 20·log10(N) decibels are added. A one-kilohertz channel step instead of ten means an N ten times larger and phase noise exactly twenty decibels worse. That is the central limitation of a classic synthesiser.

reference÷RRPDKφfilterR1 C1VCOKvcooutput÷NN
The noise of the reference and the phase detector is multiplied by N² — that is the price of a fine step
Reference frequency (MHz)
Channel step (Hz)
Output frequency (MHz)
VCO sensitivity (MHz/V)
Charge pump current (mA)
Filter capacitance C1 (nF)
Filter impedance R1 (kΩ)
Phase detector noise floor (dBc/Hz)
Dividers
Factor N
Factor R
Comparison frequency
Loop
Natural frequency ωn
Damping factor ζ
Recommended loop bandwidth (fpd/10)
Approximate lock time
Phase noise
Divider contribution 20·log10(N)
Noise inside the loop bandwidth

📐 The formulas​

Dividers:

N = f_out / f_step          R = f_ref / f_step
Comparison frequency fpd = f_step

Gain constants:

Kvco[rad/(s·V)] = 2π · Kvco[Hz/V]
Kφ[A/rad] = I_pump / 2π

A second-order loop (R1 + C1):

ωn = √( Kφ · Kvco / (N · C1) )
ζ  = R1·C1·ωn / 2
Loop bandwidth ≈ ωn/(2π)
Lock time ≈ 4/(ζ·ωn)

In-band phase noise:

L(f) = PN_floor + 20·log10(N) + 10·log10(fpd)

A check point:​

I = 5 mA, Kvco = 20 MHz/V, N = 100, C1 = 10 nF, R1 = 1 kΩ → ωn = 316,230 rad/s = 50.3 kHz, ζ = 1.58. Phase noise with a floor of −220 dBc/Hz and fpd = 1 MHz: −120 dBc/Hz.

Where this calculator stops:
  • A second-order model: real synthesisers use a third- or fourth-order filter with an extra pole
  • The loop bandwidth must not exceed a tenth of the comparison frequency, and the calculator warns you
  • Divider delay is not accounted for, and at high frequencies it shifts the phase and degrades stability
  • VCO noise outside the loop bandwidth is not calculated: take it from the datasheet

🎯 In practice​

  • Designing a synthesiser for a homebrew transceiver.
  • Understanding why a fine channel step is noisy — and exactly what it costs.
  • Choosing a loop filter for the synthesiser chip you have.
Practical advice:
  1. A ζ of 0.7–1.0 is the optimum: less rings, more locks slowly.
  2. A loop bandwidth of a tenth of the comparison frequency is the working rule for stability.
  3. The VCO supply must be clean: any ripple turns into sidebands.
  4. A fractional-N divider removes the conflict between step and bandwidth — at the cost of quantisation noise.

© 2026 UR3PKI · CyberDev.Space · Content licensed under CC BY-NC-SA 4.0.

How to cite this calculator
UR3PKI. «PLL calculator: dividers and loop filter». CyberDev.Space. https://cyberdev.space/en/radio/calculators/others/pll (licence CC BY-NC-SA 4.0).

The licence lets you use this material freely, including in teaching materials, but only with attribution to the author and a link to the source.

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